Sub-volt ferroelectric capacitor survives a trillion switching cycles at nanosecond speeds

Researchers at Seoul National University have built a ferroelectric capacitor that switches at 0.6 V and keeps its two stored states distinguishable after 1 trillion cycles without hard electrical breakdown. The team, led by Professor Min Hyuk Park, reports the work in Nature Communications. By engineering the boundary between electrode and ferroelectric film, they eased the so-called speed-endurance dilemma that has limited ferroelectric memory.

The trade-off in ferroelectric memory

DRAM stores bits as charge in capacitors. That charge leaks, so it must be refreshed regularly, which costs power. Ferroelectric memory instead records a bit in the direction of polarization, which persists after the applied field is removed. In principle, this reduces the refresh burden, a concern for high-bandwidth memory in AI servers and for low-power DRAM in mobile devices.

The material studied is hafnia-zirconia (HZO), which combines two oxides already used in chip manufacturing and can be deposited as uniform films a few nanometres thick by atomic layer deposition. The difficulty is that faster polarization switching normally needs a higher voltage, and higher voltage stresses the device and shortens its life. Thinning the film does not fully solve this, because the electrode interface matters more as the film shrinks.

Engineering the interface

The team used atomic layer deposition to control the crystallographic orientation and surface properties of the titanium nitride electrode. They also suppressed interfacial oxidation, giving a thin, uniform interfacial layer. This reduced voltage loss at the interface and allowed polarization to switch more uniformly.

In a 5-nm HZO capacitor, the result was a clear polarization signal at 0.6 V. The time to switch half of the polarization was about 40 ns at 0.6 V and about 8 ns at 1 V; the paper gives measured values of 42.1 ns and 8.1 ns. Using a criterion of less than 20% polarization loss, the device endured 600 billion cycles at 0.6 V and 1 trillion at 1 V. No hard breakdown appeared at either voltage after 1 trillion cycles.

Using the depolarization field

The depolarization field inside a ferroelectric usually weakens remanent polarization and harms retention. The researchers found that in the early stage of polarization reversal, this field can instead lower the external voltage needed to switch. A model incorporating electrode and interface properties describes the effect and suggests a design strategy for thin films.

Switching also tended to become faster as device area decreased. From their measurements, the authors predict that nanometre-scale devices could switch in nanoseconds at low voltage, and the paper projects sub-nanosecond reversal at capacitor dimensions relevant to DRAM. These are projections, not measurements on such devices.

Towards DRAM-like cells

Based on the one-transistor, one-capacitor layout used in DRAM, the team proposed common-plate ferroelectric memory (CP-FeRAM), in which an electrode shared by several cells is held at a constant voltage. Circuit simulations built on the measured polarization data suggested that stored information could remain distinguishable through remanent polarization even after the stored charge had fallen. A test array of capacitors sharing a common electrode behaved uniformly, with no significant polarization loss in a device after repeated cycling of its neighbours.

Large remanent polarization may also help preserve a readable signal as cells shrink, which would support denser integration. The authors suggest the principles could apply to low-power embedded memory placed alongside computing circuits as well.

Caveats and next steps

The results come from test capacitors and a small test array, with architecture-level behaviour assessed mainly by simulation. The source does not report full memory chips, retention over long periods or manufacturing yield. The claim of a leading combination of voltage, speed and endurance is the authors' own comparison with earlier reports.

Further work will need to show whether the interface-engineering approach holds at scaled dimensions and in integrated arrays with transistors. The study involved Hanyang University, Pohang Accelerator Laboratory and Samsung Electronics. First author Dr Geun Hyeong Park plans to continue developing low-power memory devices aimed at AI semiconductors.

Source: Low-voltage capacitor combines rapid switching with a trillion cycles without breakdown (Tech Xplore, 5 November 2026).

Image: AI-generated illustration.